Integrated circuits (ICs) are what power today's electronic devices, such as, cellphones, calculators, televisions, portable computers, portable music players, etc. IC fabrication has progressed to the sub 0.25 micron design era, with tens of millions of transistors and an estimated 50 million connections on a few square centimeters of an ICs surface. This advanced level of IC fabrication involves many process steps that deposit or grow films, followed by repeated patterning to form device and interconnect structures.
Multiple level metallization is the enabling technology that permits interconnecting the millions of transistors and supporting components on individual ICs. Multiple level metallization promotes higher device density because of its efficient use of vertical space. Of course, interlayer dielectric layers (ILDs) are needed to electrically isolate these multiple metal layers. The ILDs are commonly photolithographically patterned and dry-etched to open vias for metal interconnection.
Multiple level metallization creates the need for billions of these vias. The vias are filled with metal to form electrical pathways between metal layers. The most commonly used metal for filling the vias is tungsten. Tungsten is a good plug material because of its resistance to electromigration. Tungsten is also a good plug material because of its ability to uniformly fill high-aspect ratio vias when deposited by chemical vapor deposition (CVD).
Tungsten CVD is typically deposited in blanket films. Blanket deposition deposits tungsten non-selectively on the entire wafer surface, including the via pathways. It is necessary to remove the excess blanket deposited tungsten because such excess will lead to a non-planar topography, which will adversely affect later processing steps.
Previous methods have employed a tungsten etchback process to remove the excess tungsten and leave a planarized plug. In the sub 0.25 micron device generation, planarization of tungsten by CMP is the preferred process. Unfortunately, CMP overetch at the boundary between tungsten arrays and dielectric spaces can be so severe as to cause serious recess at this region. Consequently, later deposited metal layers will be trapped within the recess during subsequent metal deposition steps. The trapped metal layers are very difficult to remove by subsequent processes (e.g.—metal-1 layer copper CMP) and can cause electrical shorts.
Thus, a need still remains for a reliable tungsten CMP process that will reduce the incidence of CMP overetch during tungsten polishing. In view of the ever increasing need to improve product yield, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.